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Research
Openings: I currently have a couple
of openings for Ph.D. graduate students (only) who have the
background in both IC design and nanoscale silicon technology. If you are
interested, welcome to come by during my office hours. For more in-depth
information, please visit the webpage of
the NIMO Group.
My research focuses on modeling and design techniques for reliable,
low-power, and high-performance systems, motivated by both evolutionary and
revolutionary advances in nanoscale technology. I am particularly interested
in the following topics:
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Compact modeling for nanoscale CMOS and
post-silicon technologies
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Physical-level design and tools for
variability and reliability
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Reliable integration of emerging technologies
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High-speed
and low-power design techniques
To explore early stage design solutions,
Predictive Technology Model (PTM) is developed for sub-45nm technology
generations, covering traditional bulk CMOS, alternative materials and structures (e.g., FinFET), and
post-silicon devices (e.g., CNT-FET). In addition, this predictive modeling
framework accurately captures emerging physical effects, such as variability and reliability. To investigate more,
welcome to visit
PTM and send me your valuable feedbacks.
Teaching
EEE 333 (F08), “HDL
and Programmable Logic”,
T/Th, 1:30-2:45pm, Office hours: T/Th, 3:00-4:00pm
EEE 333 (S08), “HDL
and Programmable Logic”,
Office hours: T/Th, 11:00-12:00pm
EEE 525 (F07), “VLSI design,” Office hours:
M/W, 2:00-3:00pm
EEE 525 (S07), “VLSI design,” Office hours: M/W, 1:30-2:30pm
EEE 598 (F06), “Modeling and Design for Nano-CMOS Technology,”
Office hours: M/W, 1:30-2:30pm
EEE 525 (S06), “VLSI design,” Office hours: M/W, 1:30-2:30pm.
EEE 425 (F05), “Digital systems and circuits,” Office hours: M/W,
1:40-3:00pm.
EEE 525 (S05), “VLSI design,” Office hours: T, 3-5pm; Th, 2-3pm.
Professional Activities
Vice-Chair, Circuit Reliability Committee, IRPS, 2009.
Co-Organizer, IEEE/ACM Workshop on Compact Variability
Modeling (CVM), 2008.
Chair, Device Modeling and Simulation Subcommittee, ICCAD,
2008.
Design Contest Chair, ISLPED 2008.
Member of the Compact Modeling Technical Committee, IEEE Electron Devices
Society, 2007 - present
Program Committee Member: DAC 2007/2008, GLSVLSI 2006-2008, ICCAD 2005-2007,
ICCD 2005-2007, ISLPED 2005-2007, ISQED 2008, SLIP 2007/2008.
Session Chair: DAC 2005/2007, ICCAD 2005/2006, ICCD 2005, ISLPED 2005/2007, ISQED
2006.
Honors
Chunhui Award for Outstanding Oversea Chinese Scholars, Ministry of
Education of China, 2008.
Best Paper Award: “Compact modeling of carbon nanotube transistor for early
stage process-design exploration,” ISLPED 2007.
IBM Faculty Award, 2007.
NSF Faculty Early Career Development (CAREER) Award, 2006.
IBM Faculty Award, 2006.
Best Paper Award: “SRAM leakage suppression by minimizing standby supply
voltage,” ISQED 2004.
Beatrice Winner Award: “Accurate in-situ measurement of peak noise and
signal delay induced by interconnect coupling,” ISSCC 2000.
Regents Fellowship, University of California, Santa Cruz, 1996.
Publications
Some of my recent publications are selected as follows. A full list is
available here.
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B. Wong, A. Mittal, Y. Cao, and G. Starr,
Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc.,
2004.
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B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T. Pileggi, R.
A. Rutenbar, and K. L. Shepard, "Digital circuit design challenges and
opportunities in the era of nanoscale CMOS," Proceedings of IEEE, vol.
96, no. 2, pp. 343-365, February 2008.
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W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S.
Krishnan, Y. Cao, “Compact modeling and simulation of circuit
reliability for 65nm CMOS technology”, IEEE Transactions on Device
and Materials Reliability, vol. 7, no. 4, pp. 509-517, December
2007.
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W. Zhao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif, K.
Nowka, Y. Cao, “Rigorous extraction of process variations for 65nm CMOS
design,” European Solid-State Circuits Conference, pp. 89-92,
2007.
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A. Balijepalli, S. Sinha, Y. Cao, “Compact modeling of
carbon nanotube transistor for early stage process-design exploration,”
International Symposium on Low Power Electronics and Design
(best
paper award), pp. 2-7, 2007.
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W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, F. Liu, S.
Vrudhula, Y. Cao, “The impact of NBTI on the performance of
combinational and sequential circuits,” Design Automation Conference,
pp. 364-369, 2007.
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R. Singhal, A. Balijepalli, A. Subramaniam, F. Liu, S.
Nassif, Y. Cao, “Modeling and analysis of non-rectangular gate for
post-lithography circuit simulation,” Design Automation Conference,
pp. 823-828, 2007.
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M. Chen, W. Zhao, F. Liu, Y. Cao, “Fast statistical
circuit analysis with finite-point based transistor model,” Design,
Automation and Test in Europe, pp. 1391-1396, 2007.
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H. Qin, R. Vattikonda, T. Trinh, Y. Cao,
J. Rabaey, “SRAM cell optimization for ultra-low power standby,” ASP
Journal of Low Power Electronics, vol. 2, no. 3, pp. 401-411,
December 2006.
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W. Zhao, Y. Cao, “New generation of
predictive technology model for sub-45nm early design exploration,” IEEE Transactions on Electron Devices, vol. 53, no. 11, pp.
2816-2823, November 2006.
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S. Bhardwaj, W. Wang, R.
Vattikonda, Y. Cao, S. Vrudhula, “Predictive modeling of the NBTI effect
for reliable design,” Custom Integrated Circuits Conference, pp.
189-192, 2006.
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R. Vattikonda, W. Wang,
Y. Cao, “Modeling and minimization of PMOS NBTI effect for robust
nanometer design,” Design Automation Conference, pp. 1047-1052,
2006.
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H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, “SRAM
leakage suppression by minimizing standby supply voltage,” International Symposium on Quality Electronic Design (best
paper award), pp. 55-60, 2004.
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Y. Cao, R. A. Groves, N. D. Zamdmer, J.
Plouchart, R. A. Wachnik, X. Huang, T. King, and C. Hu,
“Frequency-independent equivalent circuit model for on-chip spiral
inductors,” IEEE Journal of Solid-State Circuits, vol. 38, no. 3,
pp. 419-426, March 2003.
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